Liquid crystal displays (LCDs) have become mainstream products in present flat panel displays due to the characteristics of small size, low power consumption, no radiation and the like. At present, with wide application of high-resolution and small-sized liquid crystal displays, liquid crystal displays with low power consumption have become a general trend.
An array substrate is an important part of a liquid crystal display, and is also a key component for displaying. With the development of technology, people try to make many improvements on the array substrate to reduce the power consumption of the liquid crystal display.
For example, with respect to an array substrate of a liquid crystal display of a High Advanced Super Dimension Switch (HADS) mode, as shown in FIG. 1, a common electrode is arranged above a data line, and the common electrode and the data line have mutually superposed parts on the spatial position, so that a capacitor is formed between the common electrode and the data line in the array substrate during displaying. The higher the capacitance of the capacitor is, the higher the power consumption of the array substrate is. Generally, an organic insulating layer is additionally arranged between the common electrode and the data line of the array substrate to reduce the power consumption of the array substrate and even the whole display. The organic insulating layer enables the distance between the common electrode and the data line to be increased and the capacitance between the common electrode and the data line to be reduced, so that the power consumption of the array substrate is reduced.
Generally, signal test is needed after the array substrate is manufactured. A signal test structure is generally formed in a non-display area of the array substrate, and is manufactured together with a display structure in a display area of the array substrate. Part of the layer structure in the display area also extends to the non-display area, e.g. an organic insulating layer, a gate insulating layer, a passivation layer and the like, so that additional process steps are not added during manufacturing, and the mismatch gap between the non-display area and the display area may be reduced so that signal exchanging between the non-display area and the display area is facilitated.
Generally, the signal test includes gate line signal test and data line signal test, namely a gate line test signal is applied to a gate line and a data line test signal is applied to a data line through the test structure to detect whether the array substrate operates normally. In the prior art, as shown in FIG. 1, the gate line test signal is applied via a gate line signal input electrode 21 arranged in a non-display area 02, and the data line test signal is applied via a data line signal input electrode 22 arranged in the non-display area 02. The gate line signal input electrode 21 is arranged on the same layer as the gate line, a gate insulating layer 8, an organic insulating layer 9 and a passivation layer 10 which extend from a display area 01 are sequentially arranged above the gate line signal input electrode 21, and a first introduction electrode 61 is formed on the passivation layer 10 and is electrically connected with the gate line signal input electrode 21 via a via hole I 010 penetrating through the gate insulating layer 8, the organic insulating layer 9 and the passivation layer 10; and the data line signal input electrode 22 is arranged on the same layer as the data line, the organic insulating layer 9 and the passivation layer 10 which extend from the display area 01 are sequentially arranged above the data line signal input electrode 22, and a second introduction electrode 62 is formed on the passivation layer 10 and is electrically connected with the data line signal input electrode 22 via a via hole II 020 penetrating through the organic insulating layer 9 and the passivation layer 10, wherein the first introduction electrode 61 and the second introduction electrode 62 are used for introducing the test signals to the gate line signal input electrode 21 and the data line signal input electrode 22 respectively.
In the manufacturing process of the above-mentioned array substrate, as shown in FIG. 2, for example, when the via hole I 010 correspondingly located above the gate line signal input electrode 21 is formed, an organic insulating layer via hole is formed in the organic insulating layer 9; and then a passivation layer via hole is formed in the passivation layer 10 and a gate insulating layer via hole is formed in the gate insulating layer 8 at the same time by one dry etching process. Because the aperture diameter (namely the aperture diameter r of the via hole in the passivation layer 10), corresponding to the exposed and developed part of a via hole to be formed, of the passivation layer 10 is greater than the aperture diameter R of the organic insulating layer via hole, when patterns of the passivation layer via hole and the gate insulating layer via hole are formed by one dry etching process, the hole wall of the organic insulating layer via hole is easily partially etched off again to form a gap 14 in the organic insulating layer via hole shown in FIG. 2. As a result, in the subsequent manufacturing process of the first introduction electrode 61, when extending to the organic insulating layer via hole, the first introduction electrode 61 is virtually connected with or disconnected from the gate line signal input electrode 21, then the test signals cannot be input, and normal test of the array substrate cannot be realized.